Clock Divider Bug

[ColinP]

I had a mysterious problem with the stock Clock Divider. It took me some time to figure it out but the reset doesn't do what one might expect.

ClockDividerTest.png (31.99 KiB) Viewed 1234 times

Red = clock input
Yellow = expected behaviour
Green = Clock Divider behaviour
Cyan = reset trigger

This is with DIVIDE BY set to 4

If you count the number of clocks after the reset before the divider output goes high it's 4 for the yellow trace but 5 for CA's Clock Divider.

It's still dividing by 4 once it gets over the reset miscount so it appears to be resetting to -1 instead of 0.

[seal58]

Don't think, this is a regular binary counter divider. It's not. To be honest, one could expect that and I had lots of trouble with it. That's why I created my own Multi Divider finally.

On the CA Clock Divider, a reset pulse resets output instantly. Even next clock 0/1slope sets output on and then every further Nth clock pulse does the same.

Together with sequencers Clock Divider's behaviour drived me crasy. To get a synchronuous clock, I used double frequency master clock and used at least one "Clock Divider" with 2:1 division ratio as master clock source for my presets. In this case it is good, that between a reset pulse and first "internal master clock" pulse there is a little interval.

Summery: That is not a bug - it's only "different".
Developers will have had their reasons to create the divider that way. So if you use several dividers in parallel or series, after a reset all dividers start with a pulse. That might be an advantage in distinct purposes.

[ColinP]

I would argue that the purpose of a clock divider is to divide clocks by counting clock triggers and the point of having a reset input is so that one can use the divider to count to a specific number.

CA's clock divider behaves as it should except that it resets one step out.

Here's my test rig...

ClockDividerRig1.png (333.16 KiB) Viewed 1223 times

And I can simulate the CA Clock Divider behaviour by shifting the pattern so that it's one step out i.e. resetting to -1 rather than 0...

ClockDividerRig2.png (328.49 KiB) Viewed 1223 times

[ColinP]

Thinking about this a bit further Roland, you are right to describe it as "different" rather than a bug.

Both approaches are valid it's just that I'd rather have a divider that returns a rising edge N clocks after I reset it than one that returns a rising edge after it's counted to one.

[seal58]

Well Colin, there are commonly different opinions referred to RESET.
When a sequencer gets a RESET, mostly it goes to step one. That's not what I expect with a sequencer. I wanna a sequencer to go to step one only when it gets first trigger pulse. So this is the style I built my sequencer modules.

More conveniant would be a users choice between both reset variants, as with that Clock Divider as with any sequencer.

[ColinP]

Yes, the off state for a sequencer is a problem in a clock based system.

The reason that LSSP uses V/Bar is that it solves almost all of the problems. 1 V is the first position. 0 V means off and in this case a sequencer does not really have a position. An off sequencer outputs 0 V so can be merged with other sequencers without the need for switches. Sequencers have no internal count state so there's no need for reset connections. Position is voltage rather than clock determined so self-healing under glitches, repatching or race conditions. Sequencers can go backwards or jump to intermediate positions. Time division is just arithmetic on voltage so returns to sync automatically on change. Finally position has sample precision.

Anyway back to the Clock Divider, what I was trying to do was use it to make an N-Step sequencer stop after playing N times by clocking a Clock Divider set to divide by N with the End Of Cycle trigger. But on first run instead of playing N times it plays just once.

However I've figured out how to work around the problem using just modules from Core. It's a bit clunky but it works...

ClockDividerWorkaround.png (305.78 KiB) Viewed 1193 times

[Steve W]

[withdrawn]